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FEDL9208-02 issue date: nov. 16, 2009 ml9208-xx 5 ? 7 dot character ? 16-digit display controll er/driver with character ram 1/33 general description the ml9208-xx is a dot matrix vacuum fluorescent display tube controller driver ic which displays characters, numerics and symbols. dot matrix vacuum fluorescent display tube drive signals are generated by serial data sent from a micro-controller. a display system is easily realized by internal rom and ram for character display. features ? logic power supply and vacuum fluorescent display tube drive power supply (v dd ) : 3.3 v ? 10% or 5.0 v ? 10% ? fluorescent display tube drive power supply (v fl ) : v dd ?20 v to v dd ?42 v ? vfd driver output current (vfd driver output can be connect ed directly to the fluorescent display tube. no pull-down resistor is required.) - segment driver (seg1 to seg35) : ?6 ma (v fl = v dd ?42 v) - segment driver (ad1 and ad2) : ?15 ma (v fl = v dd ?42 v) - grid driver (com1 to com16) : ?30 ma (v fl = v dd ?42 v) ? general output port output current - output driver (p1 and p2) : ? 1 ma (v dd = 3.3 v ? 10%) ? 2 ma (v dd = 5.0 v ? 10%) ? content of display - cgrom 5 ? 7 dots : 248 types (character data) - cgram 5 ? 7 dots : 8 types (character data) - adram 16 (display digit) ? 2 bits (symbol data) - dcram 16 (display digit) ? 8 bits (register for character data display) - general output port 2 bits (static operation) ? display control function - display digit : 9 to 16 digits - display duty (contrast adjustment) : 8 stages - all lights on/offs ? 3 interfaces with microcontroller : da, cs , cp (4 interfaces when reset is added) ? 1-byte instruction execution (excluding data write to ram) ? built-in oscillation circuit (external r and c) ? package options: 64-pin plastic qfp (qfp64-p-1414-0.80-bk) (ml9208-xxga) 64-pin plastic ssop (ssop64-p-525-0.80-k) (ml9208-xxmb)
FEDL9208-02 ml9208 2/33 block diagram v dd gnd v fl r ese t da cp cs osc0 osc1 seg1 seg35 ad1 ad2 p1 p2 com1 com16 dcram 16w ? ? ? shift register command decoder control circuit timing generator 1 oscillator timing generator 2 digit control duty control grid driver port driver ad driver segment driver write address counter read address counter address selector cgrom 248w ?
FEDL9208-02 ml9208 3/33 pin configuration (top view) 64-pin plastic qfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 com1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v fl com16 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 seg4 seg3 seg2 seg1 ad1 ad2 p2 p1 v dd da c p c s r eset osc1 osc0 gnd
FEDL9208-02 ml9208 4/33 64-pin plastic ssop 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 30 31 32 45 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 44 43 42 41 40 39 38 37 36 35 34 33 seg16 p1 p2 ad2 ad1 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 com6 v dd da c p c s r eset osc1 osc0 gnd v fl com16 com15 com14 com13 com12 com11 com10 com9 com8 com7 com5 com4 com3 com2 com1 seg35 seg34 seg33 seg32 seg31 seg30 seg29
FEDL9208-02 ml9208 5/33 pin description pin qfp ssop symbol type connects to description 1 to 31, 61 to 64 5 to 39 seg1 to 35 o fluorescent tube anode electrode fluorescent display tube anode electrode drive output. directly connected to fluorescent display tube and a pull-down resistor is not necessary. i oh > ?6 ma 32 to 47 40 to 55 com1 to 16 o fluorescent tube grid electrode fluorescent display tube grid electrode drive output. directly connected to fluorescent display tube and a pull-down resistor is not necessary. i oh > ?30 ma 59, 60 3, 4 ad1, ad2 o fluorescent tube anode electrode fluorescent display tube anode electrode drive output. directly connected to fluorescent display tube and a pull-down resistor is not necessary. i oh > ?15 ma 57, 58 1, 2 p1, p2 o led drive control pins general port output. output of these pins in static operation, so these pins can drive the led. 56 64 v dd 49 57 gnd 48 56 v fl ? power supply v dd -gnd are power supplies for internal logic. v dd -v fl are power supplies for driving fluorescent tubes. apply v fl after v dd is applied. 55 63 da i microcontroller serial data input (positive logic). input from lsb. 54 62 cp i microcontroller shift clock input. serial data is shifted on the rising edge of cp . 53 61 cs i microcontroller chip select input. serial data transfer is disabled when cs pin is ?h? level. reset input. ?low? initializes all the functions. initial status is as follows. ? address of each ram ???? address ?00?h ? data of each ram ?????????? content is undefined ? display digit ????????????????????? 16 digits ? contrast adjustment ??????? 8/16 ? all lights on or off ??????? off mode ? all outputs ????????????????????????? ?low? level 52 60 reset i microcontroller or c 2 , r 2 (circuit when r and c are connected externally) see application circuit. 50 58 osc0 i external rc pin for rc oscillation. connect r and c externally. the rc time constant depends on the v dd voltage used. set the target oscillation frequency to 2 mhz. 51 59 osc1 o c 1 , r 1 (rc oscillation circuit) see application circuit. osc0 osc1 r 1 c 1 r ese t r 2 c 2
FEDL9208-02 ml9208 6/33 absolute maximum ratings parameter symbol condition rating unit supply voltage (1) v dd ? ?0.3 to 6.5 v supply voltage (2) v fl ? ?45 to v dd +0.3 v input voltage v in ? ?0.3 to v dd +0.3 v qfp 541 power dissipation p d ta ?? 25?c ssop 590 mw storage temperature t stg ? ?55 to 150 ?c i o1 com1 to 16 ?40 to 0.0 ma i o2 ad1, ad2 ?20 to 0.0 ma i o3 seg1 to 35 ?10 to 0.0 ma output current i o4 p1, p2 ?4.0 to 4.0 ma recommended operating conditions-1 when the power supply voltage is 5 v (typ.) parameter symbol condition min. typ. max. unit supply voltage (1) v dd ? 4.5 5.0 5.5 v supply voltage (2) v fl ? ?36.5 ? ?20 v high level input voltage v ih all input pins excluding osc0 pin 0.7 v dd ? ? v low level input voltage v il all input pins excluding osc0 pin ? ? 0.3 v dd v cp frequency f c ? ? ? 2.0 mhz oscillation frequency f osc r 1 = 3.3 k ? , c 1 = 39 pf 1.5 2.0 2.5 mhz frame frequency f fr digit = 1 to 16, r 1 = 3.3 k ? , c 1 = 39 pf 183 244 305 hz operating temperature t op ? ?40 ? 85 ?c
FEDL9208-02 ml9208 7/33 recommended operating conditions-2 when the power supply voltage is 3.3 v (typ.) parameter symbol condition min. typ. max. unit supply voltage (1) v dd ? 3.0 3.3 3.6 v supply voltage (2) v fl ? ?38.4 ? ?20 v high level input voltage v ih all input pins excluding osc0 pin 0.8 v dd ? ? v low level input voltage v il all input pins excluding osc0 pin ? ? 0.2 v dd v cp frequency f c ? ? ? 2.0 mhz oscillation frequency f osc r 1 = 3.3 k ? , c 1 = 39 pf 1.5 2.0 2.5 mhz frame frequency f fr digit = 1 to 16, r 1 = 3.3 k ? , c 1 = 39 pf 183 244 305 hz operating temperature t op ? ?40 ? 85 ?c electrical characteristics dc characteristics-1 (v dd = 5.0 v ? 10%, v fl = v dd ?42 v, ta = ?40 to +85 ? c, unless otherwise specified) parameter symbol applied pin condition min. max. unit high level input voltage v ih cs , cp , da, reset ? 0.7 v dd ? v low level input voltage v il cs , cp , da, reset ? ? 0.3 v dd v high level input current i ih cs , cp , da, reset v ih = v dd ?1.0 1.0 a low level input current i il cs , cp , da, reset v il = 0.0 v ?1.0 1.0 a v oh1 com1 to 16 i oh1 = ?30 ma v dd ?1.5 ? v v oh2 ad1, ad2 i oh2 = ?15 ma v dd ?1.5 ? v v oh3 seg1 to 35 i oh3 = ?6 ma v dd ?1.5 ? v high level output voltage v oh4 p1, p2 i oh4 = ?2 ma v dd ?1.0 ? v v ol1 com1 to 16 ad1, ad2 seg1 to 35 ? ? v fl +1.0 v low level output voltage v ol2 p1, p2 i ol1 = 2 ma ? 1.0 v i dd1 duty = 15/16 digit = 1 to 16 all output lights on ? 4 ma current consumption i dd2 v dd f osc = 2 mhz, no load duty = 8/16 digit = 1 to 9 all output lights off ? 3 ma
FEDL9208-02 ml9208 8/33 dc characteristics-2 (v dd = 3.3 v ? 10%, v fl = v dd ?42 v, ta = ?40 to +85 ? c, unless otherwise specified) parameter symbol applied pin condition min. max. unit high level input voltage v ih cs , cp , da, reset ? 0.8 v dd ? v low level input voltage v il cs , cp , da, reset ? ? 0.2 v dd v high level input current i ih cs , cp , da, reset v ih = v dd ?1.0 1.0 a low level input current i il cs , cp , da, reset v il = 0.0 v ?1.0 1.0 a v oh1 com1 to 16 i oh1 = ?30 ma v dd ?1.5 ? v v oh2 ad1, ad2 i oh2 = ?15 ma v dd ?1.5 ? v v oh3 seg1 to 35 i oh3 = ?6 ma v dd ?1.5 ? v high level output voltage v oh4 p1, p2 i oh4 = ?1 ma v dd ?1.0 ? v v ol1 com1 to 16 ad1, ad2 seg1 to 35 ? ? v fl +1.0 v low level output voltage v ol2 p1, p2 i ol1 = 1 ma ? 1.0 v i dd1 duty = 15/16 digit = 1 to 16 all output lights on ? 3 ma current consumption i dd2 v dd f osc = 2 mhz, no load duty = 8/16 digit = 1 to 9 all output lights off ? 2 ma
FEDL9208-02 ml9208 9/33 ac characteristics-1 (v dd = 5.0 v ? 10%, v fl = v dd ?42 v, ta = ?40 to +85 ? c, unless otherwise specified) parameter symbol condition min. max. unit cp frequency f c ? ? 2.0 mhz cp pulse width t cw ? 250 ? ns da setup time t ds ? 250 ? ns da hold time t dh ? 250 ? ns cs setup time t css ? 250 ? ns cs hold time t csh r 1 = 3.3 k ? , c 1 = 39 pf 16 ? ? s cs wait time t csw ? 250 ? ns data processing time t doff r 1 = 3.3 k ? , c 1 = 39 pf 8 ? ? s reset pulse width t wres when reset signal is input from microcontroller etc. externally 250 ? ns when reset signal is input from microcontroller etc. externally 250 ? ns reset time t rson r 2 = 1.0 k ? , c 2 = 0.1 ? f ? 200 ? s da wait time t rsoff ? 250 ? ns t r t r = 20 to 80% ? 2.0 ? s all output slew rate t f c l = 100 pf t f = 80 to 20% ? 2.0 ? s v dd rise time t prz when mounted in the unit ? 100 ? s v dd off time t pof when mounted in the unit, v dd = 0.0 v 5.0 ? ms ac characteristics-2 (v dd = 3.3 v ? 10%, v fl = v dd ?42 v, ta = ?40 to +85 ? c, unless otherwise specified) parameter symbol condition min. max. unit cp frequency f c ? ? 2.0 mhz cp pulse width t cw ? 250 ? ns da setup time t ds ? 250 ? ns da hold time t dh ? 250 ? ns cs setup time t css ? 250 ? ns cs hold time t csh r 1 = 3.3 k ? , c 1 = 39 pf 16 ? ? s cs wait time t csw ? 250 ? ns data processing time t doff r 1 = 3.3 k ? , c 1 = 39 pf 8 ? ? s reset pulse width t wres when reset signal is input from microcontroller etc. externally 250 ? ns when reset signal is input from microcontroller etc. externally 250 ? ns reset time t rson r 2 = 1.0 k ? , c 2 = 0.1 ? f ? 200 ? s da wait time t rsoff ? 250 ? ns t r t r = 20 to 80% ? 2.0 ? s all output slew rate t f c l = 100 pf t f = 80 to 20% ? 2.0 ? s v dd rise time t prz when mounted in the unit ? 100 ? s v dd off time t pof when mounted in the unit, v dd = 0.0 v 5.0 ? ms
FEDL9208-02 ml9208 10/33 timing diagram symbol v dd = 3.3 v ? 10% v dd = 5.0 v ? 10% v ih 0.8 v dd 0.7 v dd v il 0.2 v dd 0.3 v dd ? da ta timing ? reset ti ming ? o utput timing c s c p da t css t ds t dh t doff t cw t cw t csh t csw valid valid valid valid v ih v ih f c v il v il v ih v il v dd r eset da t prz t rson t rsoff t pof t wres when external r and c are connected when input externally 0.8 v dd v ih 0.0 v v il v ih v il 0.5 v dd t rsoff = all outputs t f t r 0.8 v dd 0.2 v fl
FEDL9208-02 ml9208 11/33 ? d igit output timing (for 16-digit display, at a duty of 15/16) ad1, 2 seg1-35 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 v fl t 1 = 1024t t 2 = 60t t 3 = 4t frame cycle display timing blank timing v dd v fl v dd t = 8/f osc (t 1 = 4.096 ms when f osc = 2.0 mhz) (t 2 = 240 ? (t 3 = 16 ?
FEDL9208-02 ml9208 12/33 functional description commands list command lsb 1st byte msb lsb 2nd byte msb b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 1 dcram data write x0 x1 x2 x3 1000c0c1c2c3c4 c5 c6 c7 c0 c5 c10 c15 c20 c25 c30 * 2nd byte c1 c6 c11 c16 c21 c26 c31 * 3rd byte c2 c7 c12 c17 c22 c27 c32 * 4th byte c3 c8 c13 c18 c23 c28 c33 * 5th byte 2 cgram data write x0 x1 x2 *0100 c4 c9 c14 c19 c24 c29 c34 * 6th byte 3 adram data write x0 x1 x2 x31100c0c1 **** * * 4 general output port set p1 p2 * * 0010 5 display duty set d0 d1 d2 *1010 6 number of digits set k0 k1 k2 *0110 7 all lights on/off l h * *1110 test mode *: don?t care xn: address specification for each ram cn: character code specification for each ram pn: general output port status specification dn: display duty specification kn: number of digits specification h: all lights on instruction l: all lights off instruction when data is written to ram (dcram, cgram, adram) continuously, addresses are internally incremented automatically. therefore it is not necessary to specify the 1st byte to write ram data for the 2nd and later bytes. note: the test mode is used for inspection before shipment. it is not a user function.
FEDL9208-02 ml9208 13/33 positional relationship between segn and adn (one digit) c0 ad1 c0 seg1 c5 seg6 c10 seg11 c15 seg16 c20 seg21 c25 seg26 c30 seg31 c1 seg2 c6 seg7 c11 seg12 c16 seg17 c21 seg22 c26 seg27 c31 seg32 c2 seg3 c7 seg8 c12 seg13 c17 seg18 c22 seg23 c27 seg28 c32 seg33 c3 seg4 c8 seg9 c13 seg14 c18 seg19 c23 seg24 c28 seg29 c33 seg34 c4 seg5 c9 seg10 c14 seg15 c19 seg20 c24 seg25 c29 seg30 c34 seg35 a dram written data. corresponds to 2nd byte cgram written data. corresponds to 2nd byte cgram written data. corresponds to 3rd byte cgram written data. corresponds to 4th byte cgram written data. corresponds to 6th byte cgram written data. corresponds to 5th byte c1 ad2
FEDL9208-02 ml9208 14/33 data transfer method and command write method disp la y control command and data are written by an 8-bit serial transfer. write timing is shown in the figure below. setting the cs pin to ?low? level enables a data transfer. data is 8 bits and is sequentially input into the da pin from lsb (lsb first). as shown in the figure below, data is read by the shift register at the rising edge of the shift clock, which is input into the cp pin. if 8-bit data is input, internal load signals are automatically generated and data is written to each register and ram. therefore it is not necessary to input load signals from the outside. setting the cs pin to ?high? disables data transfer. data input from the point when the cs pin changes from ?high? to ?low? is recognized in 8-bit units. t doff b0 lsb c s c p da b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 msb 1st byte lsb msb 2nd byte when data is written to dcram* command and address data t csh b0b1b2 b3 b4 b5 b6 b7 lsb msb 2nd byte character code data of the next address character code data * when data is written to ram (dcram, adram, cgram) continuously, addresses are internally incremented automatically. therefore it is not necessary to specify the 1st byte to write ram data for the 2nd and later bytes. reset function r es et is executed when the reset pin is set to ?l?, (when turning power on, for example) and initializes all functions. initial status is as follows. ? address of each ram ??????????????? address ?00?h ? data of each ram ????????????????????? all contents are undefined ? general output port ???????????????????? all general output ports go ?low? ? display digit ?????????????????????????????? 16 digits ? contrast adjustment ??????????????????? 8/16 ? all display lights on or off ???? off mode ? segment output ?????????????????????????? all segment outputs go ?low? ? ad output ?????????????????????????????????? all ad outputs go ?low? please set again according to ?setting flowchart? after reset.
FEDL9208-02 ml9208 15/33 description of commands and functions 1 . dcram data write (specifies the address of dcram and writes the character code of cgrom and cgram.) dcram (data control ram) has a 4-bit address to store character code of cgrom and cgram. the character code specified by dcram is converted to a 5 ? 7 dot matrix character pattern via cgrom or cgram. (the dcram can store 16 characters.) [command format] x0 x1 x2 x3 1 0 0 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte (1st) lsb msb c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (2nd) lsb msb : selects dcram data write mode and specifies dcram address (ex: specifies dcram address 0h) : specifies character code of cgrom and cgram (written into dcram address 0h) to specify the character code of cgrom and cgram continuously to the next address, specify only character code as follows. the addresses of dcram are automatically incremented. specification of an address is unnecessary.
FEDL9208-02 ml9208 16/33 c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (3rd) lsb msb c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (4th) lsb msb : specifies character code of cgrom and cgram (written into dcram address 1h) : specifies character code of cgrom and cgram (written into dcram address 2h) b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (17th) lsb msb c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (18th) lsb msb : specifies character code of cgrom and cgram (written into dcram address fh) : specifies character code of cgrom and cgram (dcram address 0h is rewritten) c0 c1 c2 c3 c4 c5 c6 c7 x0 (lsb) to x3 (msb) : dcram addresses (4 bits: 16 characters) c0 (lsb) to c7 (msb) : character code of cgrom and cgram (8 bits: 256 characters) [com positions and set dcram addresses] hex x0 x1 x2 x3 com position 0 0 0 0 0 com1 1 1 0 0 0 com2 2 0 1 0 0 com3 3 1 1 1 0 com4 4 0 0 1 0 com5 5 1 0 1 0 com6 6 0 1 1 0 com7 7 1 1 1 0 com8 8 0 0 0 1 com9 9 1 0 0 1 com10 a 0 1 0 1 com11 b 1 1 0 1 com12 c 0 0 1 1 com13 d 1 0 1 1 com14 e 0 1 1 1 com15 f 1 1 1 1 com16
FEDL9208-02 ml9208 17/33 2. cgram data write (specifies the addresses of cgram and writes character pattern data.) cgram (character generator ram) has a 3-bit address to store 5 ? 7 dot matrix character patterns. a character pattern stored in cgram can be displayed by specifying the character code (address) by dcram. the address of cgram is assigned to 00h to 07h. (all the other addresses are the cgrom addresses.) (the cgram can store 8 types of character patterns.) [command format] c0 c5 c10 c15 c20 c25c30 * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (2nd) lsb msb : specifies 1st column data (rewritten into cgram address 00h) c1 c6 c11 c16 c21 c26c31 * b0 b1 b2 b3 b4 b5 b6 b7 3rd byte (3rd) lsb msb : specifies 2nd column data (rewritten into cgram address 00h) x0 x1 x2 * 0 1 0 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte (1st) lsb msb : selects cgram data write mode and specifies cgram address. (ex: specifies cgram address 00h) c2 c7 c12 c17 c22 c27c32 * b0 b1 b2 b3 b4 b5 b6 b7 4th byte (4th) lsb msb : specifies 3rd column data (rewritten into cgram address 00h) c3 c8 c13 c18 c23 c28c33 * b0 b1 b2 b3 b4 b5 b6 b7 5th byte (5th) lsb msb : specifies 4th column data (rewritten into cgram address 00h) c4 c9 c14 c19 c24 c29c34 * b0 b1 b2 b3 b4 b5 b6 b7 6th byte (6th) lsb msb : specifies 5th column data (rewritten into cgram address 00h) to specify character pattern data continuously to the next address, specify only character pattern data as follows. the addresses of cgram are automatically incremen ted. specification of an address is therefore unnecessary. the 2nd to 6th byte (character pattern data) are regarded as one data item, so 250 ns is sufficient for t doff time between bytes.
FEDL9208-02 ml9208 18/33 c0 c5 c10 c15 c20c25c30 * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (7th) lsb msb : specifies 1st column data (rewritten into cgram address 01h) c4 c9 c14 c19 c24c29c34 * b0 b1 b2 b3 b4 b5 b6 b7 6th byte (11th) lsb msb : specifies 5th column data (rewritten into cgram address 01h) x0 (lsb) to x2 (msb) : cgram addresses (3 bits: 8 characters) c0 (lsb) to c34 (msb) : character pattern data (35 bits: 35 outputs per digit) * : don?t care [cgrom addresses and set cgram addresses] refer to romcode table hex x0 x1 x2 cgrom address 00 0 0 0 ram00(00000000b) 01 1 0 0 ram01(00000001b) 02 0 1 0 ram02(00000010b) 03 1 1 0 ram03(00000011b) 04 0 0 1 ram04(00000100b) 05 1 0 1 ram05(00000101b) 06 0 1 1 ram06(00000110b) 07 1 1 1 ram07(00000111b)
FEDL9208-02 ml9208 19/33 positional relationship between the output area of cgrom and that of cgram c0 c5 c10 c15 c20 c25 c30 c1 c6 c11 c16 c21 c26 c31 c2 c7 c12 c17 c22 c27 c32 c3 c8 c13 c18 c23 c28 c33 c4 c9 c14 c19 c24 c29 c34 area that corresponds to 2nd byte (1st column) area that corresponds to 3rd byte (2nd column) area that corresponds to 5th byte (4th column) area that corresponds to 6th byte (5th column) area that corresponds to 4th byte (3rd column) note: cgrom (character generator rom) has an 8-bit address to generate 5 ? 7 dot matrix character patterns. cgram can store 248 types of character patterns.
FEDL9208-02 ml9208 20/33 3. adram data write (specifies address of adram and writes symbol data) adram (additional data ram) has a 2-bit address to store symbol data. symbol data specified by adram is directly output without cgrom and cgram. (the adram can store 2 types of symbol patterns for each digit.) the terminal to which the contents of adram are output can be used as a cursor. [command format] c0 c1 * * * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (2nd) lsb msb : sets symbol data (written into adram address 0h) x0 x1 x2 x3 1 1 0 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte (1st) lsb msb : selects adram data write mode and specifies adram address (ex: specifies adram address 0h) to specify symbol data continuously to the next address, specify only symbol data as follows. the address of adram is automatically incremented. specification of addresses is therefore unnecessary. c0 c1 * * * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (3rd) lsb msb : sets symbol data (written into adram address 1h) c0 c1 * * * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (4th) lsb msb : sets symbol data ( written into adram address 2h ) c0 c1 * * * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (17th) lsb msb : sets symbol data (written into adram address fh) c0 c1 * * * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (18th) lsb msb : sets symbol data (adram address 0h is rewritten.) x0 (lsb) to x3 (msb) : adram addresses (4 bits: 16 characters) c0 (lsb) to c1 (msb) : symbol data (2 bits: 2-symbol data per digit) * : don?t care
FEDL9208-02 ml9208 21/33 [com positions and adram addresses] hex x0 x1 x2 x3 com position 0 0 0 0 0 com1 1 1 0 0 0 com2 2 0 1 0 0 com3 3 1 1 1 0 com4 4 0 0 1 0 com5 5 1 0 1 0 com6 6 0 1 1 0 com7 7 1 1 1 0 com8 8 0 0 0 1 com9 9 1 0 0 1 com10 a 0 1 0 1 com11 b 1 1 0 1 com12 c 0 0 1 1 com13 d 1 0 1 1 com14 e 0 1 1 1 com15 f 1 1 1 1 com16 4. general output port set (specifies the general output port status) the general output port is an output for 2-bit static operation. it is used to control other i/o devices and turn on led. (static operation) when at the ?high? level, this output becomes the v dd voltage, and when at the ?low? level, it becomes the ground potential. therefore, the fluorescent display tube cannot be driven. [command format] p1 p2 * * 0 0 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte lsb msb : selects a general output port and specifies the output status p1, p2 : general output port * : don?t care [set data and set state of general output port] p1 p2 display state of general output port 0 0 sets p1 and p2 to low 1 0 sets p1 to high and p2 to low ? (the state when power is applied or when reset is input.) 0 1 sets p1 to low and p2 to high 1 1 sets p1 and p2 to high
FEDL9208-02 ml9208 22/33 5. display duty set (writes display duty value to duty cycle register) display duty adjusts contrast in 8 stages using 3-bit data. when power is turned on or when the reset signal is input, the duty cycle register value is ?0?. always execute this instruction before turning the display on, then set a desired duty value. [command format] d0 d1 d2 * 1 0 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte lsb msb : selects display duty set mode and sets duty value d0 (lsb) to d2 (msb) : display duty data (3 bits: 8 stages) * : don?t care [relation between setup data and controlled com duty] hex d0 d1 d2 com duty 0 0 0 0 8/16 1 1 0 0 9/16 ?? (the state when power is turned on or when reset signal is input.) 2 0 1 0 10/16 3 1 1 0 11/16 4 0 0 1 12/16 5 1 0 1 13/16 6 0 1 1 14/16 7 1 1 1 15/16
FEDL9208-02 ml9208 23/33 6. number of digits set (writes the number of display digits to the display digit register) the number of digits set can display 9 to 16 digits using 3-bit data. when power is turned on or when a reset signal is input, the number of digit register value is ?0?. always execute this instruction to change the number of digits before turning the dispaly on. [command format] k0 k1 k2 * 0 1 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte lsb msb : selects the number of digit set mode and specifies the number of digit value k0 (lsb) to k2 (msb) : number of digit data (3 bits: 8 digits) * : don?t care [relation between setup data and controlled com] hex k0 k1 k2 number of digits of com 0 0 0 0 com1 to 16 1 1 0 0 com1 to 9 ? (the state when power is turned on or when reset signal is input.) 2 0 1 0 com1 to 10 3 1 1 0 com1 to 11 4 0 0 1 com1 to 12 5 1 0 1 com1 to 13 6 0 1 1 com1 to 14 7 1 1 1 com1 to 15
FEDL9208-02 ml9208 24/33 7. all display lights on/off set (turns all dispaly lights on or off) all display lights on is used primarily for display testing. all display lights off is primarily used for display blink and to prevent malfunction when power is turned on. this command cannot control the general output port. [command format] l h * * 1 1 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte lsb msb : selects all display lights on or off mode l: sets all lights off h: sets all lights on *: don?t care [set data and display state of seg and ad] l h display state of seg and ad 0 0 normal display 1 0 sets all outputs to low ? (the state when power is applied or when reset is input.) 0 1 sets all outputs to high 1 1 sets all outputs to high ? (all lights on mode has priority.)
FEDL9208-02 ml9208 25/33 setting flowchart ( p ower applying included) a pply v fl a ll display lights off number of digits setting display duty setting cgram data write mode (with address setting) cgram character code cgram is character code write ended? a nother ram to be set? general output port setting releases all display lights off mode a dram data write mode (with address setting) a dram character code a dram is character code write ended? dcram data write mode (with address setting) dcram character code dcram is character code write ended? select a ram to be used status of all outputs by reset signal input display operation mode a ddress is automaticall y incremented no no no yes yes yes yes end a ddress is automaticall y incremented a ddress is automaticall y incremented a pply v dd no
FEDL9208-02 ml9208 26/33 power-off flowchart display operation mode turn off v dd turn off v fl
FEDL9208-02 ml9208 27/33 application circuit ml9208-01 micro- controller 16 35 2 r eset v dd com1 to 16 seg1 to 35 ad1, 2 v dd gnd r 2 c 2 gnd r 1 c 1 v fl osc0 osc1 da c p c s output port p1, 2 r 3 c 3 c 4 v dd v fl zd 2 5 ?? 7-dot matrix fluorescent display tube grid (digit) anode (segment) anode (segment) heater transformer r 4 led v dd npn tr gnd gnd gnd v dd notes: 1. the v dd value depends on the power supply voltage of the microcontroller used. adjust the values of the constants r 1 , r 2 , r 4 , c 1 , and c 2 to the power supply voltage used. 2. the v fl value depends on the fluorescent display tube used. adjust the values of the constants r 3 and zd to the power supply voltage used.
FEDL9208-02 ml9208 28/33 reference data t h e figure below shows the relationship between the v fl voltage and the output current of each driver. take care that the total power consumption to be used does not exceed the power dissipation. ?30 ?25 ?20 ?15 ?10 ?5 0 ?17 ?22 ?27 ?32 ?37 ?42 output current (ma) v fl voltage (v dd ? n ) com1 to 16 (condition: v oh = v dd ? 1.5 v) ad1 and ad2 (condition: v oh = v dd ? 1.5 v) seg1 to 35 (condition: v oh = v dd ? 1.5 v) (v) (ma) v fl voltage-output current of each driver
FEDL9208-02 ml9208 29/33 ml9208-01 rom code * rom code_a is the character set for sega1 to sega35. *00000000b(00h) to 00001111b(0fh) are the cgram_a addresses. msb 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 lsb 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ram0 ram1 ram2 ram3 ram4 ram5 ram6 ram7
FEDL9208-02 ml9208 30/33 package dimensions qfp64-p-1414-0.80-bk mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5 m) package weight (g) 0.87 typ. 5 rev. no./last revised 6/feb. 23, 2001 notes for mounting the surface mount type package the surface mount type packages are very susceptible to he at in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact rohm's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). ( unit: mm )
FEDL9208-02 ml9208 31/33 ssop64-p-525-0.80-k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5 m) package weight (g) 1.34 typ. 5 rev. no./last revised 3/dec. 5, 1996 notes for mounting the surface mount type package the surface mount type packages are very susceptible to he at in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact rohm's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). ( unit: mm )
FEDL9208-02 ml9208 32/33 revision history page document no. date previous edition current edition description fedl9208-01 oct. 23, 2003 ? ? final edition 1 FEDL9208-02 nov. 16, 2009 9 9 47pf 39 pf
FEDL9208-02 ml9208 33/33 notice no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-a utomation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the pr escribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a me dical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2009 - 2011 lapis semiconductor co., ltd.

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